A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from −70°C to 125°C

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes

A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 ¿W at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.\u

Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers

Electrical Engineering, Mathematics and Computer Scienc

Wireless Communications Device Wakeup Method and System

Abstract of WO 2009044368 Disclosed are wakeable wireless communications devices, and methods for waking wireless communications devices, for use in a wireless network of such devices. The devices communicate during respectively-designated timeslots according to a communications protocol. The wireless devices include a wireless transceiver that communicates over the wireless network during device-designated timeslots, and that is operative in a reduced power mode during other timeslots. The wireless devices further include a wakeable wakeup detection circuit (106), synchronous with the device- designated TDMA timeslots to transition out of a reduced power mode, to detect valid signals during at least one of the device-designated TDMA timeslots and, in response thereto, to prompt (108) the wireless transceiver to transition out of its reduced power mode and communicate over the wireless network

High-resolution continuous-time sigma-delta converters with multi-Bbt quantization

No abstract

A Design Methodology for Wide-Band Continuous-Time MASH ΣΔ ADC Architectures

This poster presents a design methodology for wideband continuous-time MASH ΣΔ ADCs that takes into account one clock cycle delay for each comparator. This enables the design of high-speed wide-band MASH ΣΔ ADCs, with high sampling rate and low OSR. The purpose of this research is to synthesize a continuous-time MASH ΣΔ ADC architecture suitable for wideband medium resolution ADC applications. The synthesis starts form a discrete-time MASH ΣΔ ADC architecture, with one clock cycle delay modelled for each comparator [1]. Then, discrete-time to continuous-time transformation technique similar as [2] is applied to determine the design parameters of the continuous-time MASH ΣΔ ADC architecture. Extra coefficients are introduced to provide the required additional degrees of freedom. Subsequently, a wide-band continuous-time MASH ΣΔ ADC architecture is synthesized, which is robust against loop delay variations. Extensive simulation results show the robustness and the advantages of the proposed methodology. It delivers a 9-level 1-1-1 wideband MASH ΣΔ ADC topology with 3.25 times larger signal BW when compared to the traditional approach with the same total loop delay and SNDR target. Compared to the state-of-the-art [3], it enlarges the signal BW by a factor of 2 through enabling 2 times higher sampling frequency without losing DR performance. Moreover, it facilitates the design and simulation procedures. All these properties make the proposed methodology very useful for designing wide-band medium resolution ΣΔ ADCs for high performance mixed-signal applications